Get a High-performance compiled-code Verilog 2001 simulator with a FREE 6-month License. Verilog Simulator with Report window to manage log files.
Verilog Simulator Silos ™ is an easy-to-use IEEE-1364-2001 compliant Verilog simulator used by leading IC designers. An industry standard since 1986, its powerful interactive debugging features provide today’s most productive design environment for FPGA, PLD, ASIC and custom digital designs. Key Features.
IEEE-1364-2001 compliant Verilog simulator with Programming Language Interface (PLI) supports language extensions. Productive debugging environment with graphic data analyzer, trace mode, hierarchy explorer, and interactive source code editor. Embedded lint tool that can make comprehensive syntax, semantic and design rule checking with over 500 checking rules. Can check for simulation and synthesis mismatches, race condition, clock domain synchronization and more. Supports compliance testing for RTCA/DO-254, “Design Assurance Guidance for Airborne Electronic Hardware,” Appendix B.
Silvaco's strong encryption is available to protect valuable customer and third party intellectual property. Data Analyzer uses the Trace Signal Window and the Source Code Window to trace the cause of an unknown value.
Analog waveforms can be displayed in either piecewise linear format or stepping format.